1. Field of the Invention
This invention relates generally to MOS very large scale integrated (VLSI) circuits and, more particularly, to an MOS transistor-transistor logic (T.sup.2 L) input buffer circuit having a more stabilized switching point over variations in supply voltage, temperature and process parameters.
2. Description of the Prior Art
The advantages offered by NMOS technology are well known; e.g. higher density, greater yield, etc. The smaller NMOS device geometries permit a greater number of devices to be produced per unit area, or, stated another way, a single device will occupy less space. This characteristic is extremely important in the design and fabrication of complex digital integrated circuits; for example, single chip microprocessors. However, it is often necessary for such MOS circuitry to interface with other electronic circuitry fabricated in accordance with different technologies; e.g. T.sup.2 L.
T.sup.2 L output signals are generally representative of logic zero and logic one states. A T.sup.2 L logic one state may be represented by a voltage as low as two volts, and a T.sup.2 L logic zero level may be represented by a voltage of as much as 0.8 volts. Due to this relatively low input voltage swing, variations in switching points due to variations in the supply voltage (V.sub.DD), temperature and process variations could result in nonrecognition by the buffer circuit of an input voltage transition.